Generally, phase-locked loops are circuits that essentially consist of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference frequency generator. The output of the phase detector is fed back to the voltage-controlled oscillator after passing through a loop filter in order to maintain the output in phase exactly with the incoming or reference frequency.
A block diagram of a typical PLL is illustrated by FIG. 1a. A divider circuit 10 receives a signal with a reference frequency, F.sub.ref, and divides the signal by reference delay value, D.sub.ref, before passing the signal to a phase frequency detector (PFD) 12. The PFD 12 compares the frequency of the reference signal to that of the signal generated by a voltage controlled oscillator (VCO) 14, a typical example of which is illustrated in FIG. 1b. Further included are charge pump 16 which together with low pass filter (LPF) 18, usually a large capacitor, charges up the generated signal to make the phases of the reference signal and generated signal line together. Divider circuits 20 and 22 divide the generated signal by chosen delay values, D.sub.fb or D.sub.out, as the generated signal is fed back to the PFD 12 or out of the PLL.
As described, the LPF 18 is usually a large capacitor, in the range of 100-500 pF (picoFarads), which aids in reducing jittering, especially in faster signals with higher frequencies. Further aiding in the reduction of jittering is a lower charge current value. Generally, during power down mode, the large capacitor in the LPF 18 is shunt to ground. When power-up occurs, the voltage across the large capacitor needs to be charged-up above the threshold value of a MOSFET 23, FIG. 1b, typically used in the VCO 14 before the PLL can begin normal lock-in procedure. Typically, the lock-in time is very long due to the large capacitor and lower charge current value.
Accordingly, a need exists for a simple charge control scheme to reduce the lock-in time upon power-up in a PLL.